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Allwinner /D1H /UART[1] /RXDMA_STA

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Interpret as RXDMA_STA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (idle)busy 0 (ready)buffer_read_address_updating

busy=idle, buffer_read_address_updating=ready

Description

UART RXDMA Status Register

Fields

busy

0 (idle): undefined

1 (busy): undefined
buffer_read_address_updating

0 (ready): undefined

1 (busy): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data